Stream Buffer Controller
IP core for buffer management of high-speed data streams.
Overview
Stream Buffer Controller is an Enclustra IP core for buffer management of high-speed data streams. Buffering and flow control happen inside the FPGA, letting you build high-throughput data paths.
Positive ONE Group supports Stream Buffer Controller end to end: choosing the right option, providing evaluation versions, helping you obtain reference designs, and supply and long-term availability in volume production. We work in English and Japanese.
Appearance and internal structure
Key specifications
| Supported standards | - (stream buffer IP) |
|---|---|
| Supported FPGA families | AMD / Intel supported |
| Speed | Depends on configuration |
| Port configuration | - (buffer control) |
| Operating mode | High-throughput stream buffer management |
| Latency and forwarding | DMA / buffering |
| Interfaces | AXI4 / AXI4-Stream |
| Licence | Project licence |
| Deliverables | RTL, sample design and documentation |
| EDA integration | Vivado IP Integrator |
Actual resource usage (LUT, FF, BRAM), supported devices and speed grades vary by configuration. Tell us your requirements and we will give concrete figures with the quotation.
Main interfaces and applications
Main interfaces
- AXI / AXI-Stream (internal FPGA interconnect)
- Standard FPGA bus interfaces
Typical applications
- Integrating function blocks into your own FPGA design
- Shorter development and verification time
- Implementing signal processing, communication and control pipelines
Frequently asked questions
How is this IP core delivered?
It is licensed per project. An evaluation version is available so you can confirm operation on your own FPGA before production. Deliverables are a netlist or encrypted RTL, a sample design and the user manual.
Which FPGAs can Stream Buffer Controller be used with?
Built on open standards, it can be implemented on several FPGA families, primarily AMD/Xilinx. It is supplied as VHDL source and works with EDA tools such as AMD Vivado.
How is Stream Buffer Controller delivered and licensed?
It is supplied as a VHDL source IP core with a technical support package. Extensive synthesis-time and run-time parameters let you optimise FPGA resource usage, and custom development is available.
How can I evaluate Stream Buffer Controller?
You can verify operation on real hardware using evaluation kits, sample designs and SoC-e’s SocTek modules or RelyUm equipment. Some configurations allow plug-and-play evaluation.
What is the price and lead time for Stream Buffer Controller?
Pricing for Stream Buffer Controller depends on configuration, licence type, quantity and any customisation, so we quote individually. Tell us your application and quantity in the form on this page and our engineers will confirm the specification and come back with a quotation and lead time.
Related products in the Enclustra IP core line
Other models in the same product line. Select by logic capacity, I/O count and temperature grade.
See all products using Zynq UltraScale+ MPSoC ／ See all products using Zynq-7000 SoC ／ Browse by FPGA family ／ Browse by application
Ask about Stream Buffer Controller
Stream Buffer Controller is handled in Japan by Positive ONE Group, value-added reseller (VAR) for Enclustra of Switzerland. We confirm availability, quantities and pricing with the manufacturer before replying.
Because pricing depends on configuration and quantity, we do not publish prices or stock levels on this site.Request an individual quotation