Universal DSP Library
DSP IP library optimised for FPGAs, accelerating signal-processing design.
Overview
Universal DSP Library is an Enclustra library of DSP IP optimised for FPGAs. Filtering, transform and arithmetic blocks are implemented efficiently against FPGA resources, cutting the design effort for signal processing pipelines.
Positive ONE Group supports Universal DSP Library end to end: choosing the right option, providing evaluation versions, helping you obtain reference designs, and supply and long-term availability in volume production. We work in English and Japanese.
Appearance and internal structure
Key specifications
| Supported standards | - (DSP library) |
|---|---|
| Supported FPGA families | Vendor-independent VHDL source |
| Speed | Depends on configuration |
| Port configuration | - (function library) |
| Operating mode | DSP components such as FIR, FFT and filters |
| Latency and forwarding | Parameterised (depends on configuration) |
| Interfaces | AXI4-Stream |
| Licence | Library licence |
| Deliverables | RTL source, documentation and testbench |
| EDA integration | Vivado / Quartus / Libero / Diamond |
Actual resource usage (LUT, FF, BRAM), supported devices and speed grades vary by configuration. Tell us your requirements and we will give concrete figures with the quotation.
Main interfaces and applications
Main interfaces
- AXI / AXI-Stream (internal FPGA interconnect)
- Standard FPGA bus interfaces
Typical applications
- Integrating function blocks into your own FPGA design
- Shorter development and verification time
- Implementing signal processing, communication and control pipelines
Frequently asked questions
How is this IP core delivered?
It is licensed per project. An evaluation version is available so you can confirm operation on your own FPGA before production. Deliverables are a netlist or encrypted RTL, a sample design and the user manual.
Which FPGAs can Universal DSP Library be used with?
The VHDL source is vendor-independent. For AMD (Xilinx), an integration flow is provided as Vivado IPI blocks. For other vendors we can share only what we have confirmed. Please ask us if your target is already fixed.
How is Universal DSP Library delivered and licensed?
It is supplied as a VHDL source IP core with a technical support package. Extensive synthesis-time and run-time parameters let you optimise FPGA resource usage, and custom development is available.
How can I evaluate Universal DSP Library?
A three-month evaluation licence can be requested. Please contact us to discuss the configuration.
What is the price and lead time for Universal DSP Library?
Pricing for Universal DSP Library depends on configuration, licence type, quantity and any customisation, so we quote individually. Tell us your application and quantity in the form on this page and our engineers will confirm the specification and come back with a quotation and lead time.
Related products in the Enclustra IP core line
Other models in the same product line. Select by logic capacity, I/O count and temperature grade.
See all products using Zynq UltraScale+ MPSoC ／ See all products using Zynq-7000 SoC ／ Browse by FPGA family ／ Browse by application
Ask about Universal DSP Library
Universal DSP Library is handled in Japan by Positive ONE Group, value-added reseller (VAR) for Enclustra of Switzerland. We confirm availability, quantities and pricing with the manufacturer before replying.
Because pricing depends on configuration and quantity, we do not publish prices or stock levels on this site. Request an individual quotation
Design environment
- Portability
- Vendor-independent VHDL source
- Integration
- AMD (Xilinx) integration available (Vivado IPI block)
- Design tools
- AMD Vivado
- Evaluation
- Three-month evaluation licence (on request)
- Licence
- Site licence (one location, radius under 5 km)