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Universal Drive Controller

Motor drive control IP

Motor and drive control IP core for industrial motion control.

Universal Drive ControllerCommunication IP coreEnclustra
FPGA
Motor drive control IP
Memory
Temp
Size
IP cores
Overview

Overview

Universal Drive Controller is an Enclustra IP core for motor and drive control. It implements the control loops needed for industrial motion control inside the FPGA, giving low-latency, high-precision motor drive.

Positive ONE Group supports Universal Drive Controller end to end: choosing the right option, providing evaluation versions, helping you obtain reference designs, and supply and long-term availability in volume production. We work in English and Japanese.

Diagram

Appearance and internal structure

Universal Drive Controller block diagram and internal structure
Official block diagram from the manufacturer
SYSTEM CONNECTION — Universal Drive ControllerUser logicYour logicUniversal Drive ControllerIP CoreEthernetNetworkAXIMAC
System connection diagram
IP specification

Key specifications

Universal Drive Controller key specifications
Supported standards- (motor control IP)
Supported FPGA familiesAMD / Intel supported
SpeedDepends on configuration
Port configuration- (control IP)
Operating modeDC, BLDC and stepper motors, vector control and space vector PWM
Latency and forwardingDeterministic control loops
InterfacesAXI4-Lite / AXI4-Stream, PWM and encoder interfaces
LicenceProject licence
DeliverablesRTL, sample design and documentation
EDA integrationVivado IP Integrator

Actual resource usage (LUT, FF, BRAM), supported devices and speed grades vary by configuration. Tell us your requirements and we will give concrete figures with the quotation.

Interfaces and applications

Main interfaces and applications

Main interfaces

  • AXI / AXI-Stream (internal FPGA interconnect)
  • Standard FPGA bus interfaces

Typical applications

  • Integrating function blocks into your own FPGA design
  • Shorter development and verification time
  • Implementing signal processing, communication and control pipelines
FAQ

Frequently asked questions

How is this IP core delivered?

It is licensed per project. An evaluation version is available so you can confirm operation on your own FPGA before production. Deliverables are a netlist or encrypted RTL, a sample design and the user manual.

Which FPGAs can Universal Drive Controller be used with?

Built on open standards, it can be implemented on several FPGA families, primarily AMD/Xilinx. It is supplied as VHDL source and works with EDA tools such as AMD Vivado.

How is Universal Drive Controller delivered and licensed?

It is supplied as a VHDL source IP core with a technical support package. Extensive synthesis-time and run-time parameters let you optimise FPGA resource usage, and custom development is available.

How can I evaluate Universal Drive Controller?

You can verify operation on real hardware using evaluation kits, sample designs and SoC-e’s SocTek modules or RelyUm equipment. Some configurations allow plug-and-play evaluation.

What is the price and lead time for Universal Drive Controller?

Pricing for Universal Drive Controller depends on configuration, licence type, quantity and any customisation, so we quote individually. Tell us your application and quantity in the form on this page and our engineers will confirm the specification and come back with a quotation and lead time.

Ask about Universal Drive Controller

Universal Drive Controller is handled in Japan by Positive ONE Group, value-added reseller (VAR) for Enclustra of Switzerland. We confirm availability, quantities and pricing with the manufacturer before replying.

Because pricing depends on configuration and quantity, we do not publish prices or stock levels on this site.Request an individual quotation