IP core (implemented in your own FPGA), embedded module (mounted on your board), expansion card (plugged into a PC), or ready-built equipment (simply installed). Development effort and flexibility differ greatly between them.
See how to choose a deployment option →HPS — HSR/PRP Switch
Full hardware implementation of zero-recovery-time HSR/PRP redundancy (IEC 62439-3 Ed.4.0). Cut-through forwarding gives very low latency, for power system equipment.
The PDF is the official SoC-e product brochure. It overlaps with the specification table on this page, butthe manufacturer’s official PDF is authoritative, and this page is a summary of it. Where the two differ, the PDF takes precedence; please contact us.
Overview
HPS — HSR/PRP Switch is a soft IP in the SocTek IP core range from SoC-e, aimed at high-availability Ethernet. HSR (High-availability Seamless Redundancy) and PRP (Parallel Redundancy Protocol) are zero-recovery-time redundancy schemes: traffic keeps flowing even when one path fails. They are the standard choice where not even a momentary loss of communication is acceptable, such as power system protection. HPS — HSR/PRP Switch implements this as hardware logic inside the FPGA.
It fits in modest resources, so it can be implemented comfortably even on small, low-cost FPGAs.
Positive ONE Group supports HPS — HSR/PRP Switch end to end: choosing the right option, providing evaluation versions, helping you obtain reference designs, and supply and long-term availability in volume production. We work in English and Japanese.
Appearance and internal structure
Key specifications
| Supported standards | IEC 62439-3 (HSR/PRP), IEEE 1588 |
|---|---|
| Supported FPGA families | AMD Zynq UltraScale+, Zynq-7000 and Kintex, plus Intel |
| Speed | 10/100/1000 Mbps |
| Port configuration | Ring port A / B plus interlink (three ports as standard) |
| Operating mode | DANH / DANP / RedBox / HSR-SAN / HSR-PRP conversion / QuadBox |
| Latency and forwarding | Cut-through (no store-and-forward delay between rings) |
| Interfaces | AXI4-Lite (configuration), (R)GMII (per port) |
| Licence | Project licence, evaluation version available |
| Deliverables | Netlist or encrypted RTL, sample design and user manual |
| EDA integration | Vivado IP Integrator (port count and QoS set in the GUI, no RTL changes required) |
Actual resource usage (LUT, FF, BRAM), supported devices and speed grades vary by configuration. Tell us your requirements and we will give concrete figures with the quotation.
Main interfaces and applications
Main interfaces
- Ethernet MAC / PHY interface
- AXI (internal FPGA interconnect)
Typical applications
- Protection relays and control equipment for substation automation (IEC 61850)
- On-board and trackside railway signalling systems
- High-availability control networks in industrial plants
Frequently asked questions
How is this IP core delivered?
It is licensed per project. An evaluation version is available so you can confirm operation on your own FPGA before production. Deliverables are a netlist or encrypted RTL, a sample design and the user manual.
Which FPGAs can HPS — HSR/PRP Switch be used with?
Built on open standards, it can be implemented on several FPGA families, primarily AMD/Xilinx. It is supplied as VHDL source, works with EDA tools such as AMD Vivado, and fits on low-cost devices.
How is HPS — HSR/PRP Switch delivered and licensed?
It is supplied as a VHDL source IP core with a technical support package. Extensive synthesis-time and run-time parameters let you optimise FPGA resource usage, and custom development is available.
How can I evaluate HPS — HSR/PRP Switch?
You can verify operation on real hardware using evaluation kits, sample designs and SoC-e’s SocTek modules or RelyUm equipment. Some configurations allow plug-and-play evaluation.
What is the price and lead time for HPS — HSR/PRP Switch?
Pricing for HPS — HSR/PRP Switch depends on configuration, licence type, quantity and any customisation, so we quote individually. Tell us your application and quantity in the form on this page and our engineers will confirm the specification and come back with a quotation and lead time.
IP core configuration and integration
Detailed technical specification
Detailed specification based on the official SoC-e datasheet (SocTek IP Cores / HPS). Order code: S-3111.
Communication interfaces
- Integrates a 10/100/1000M MAC and supports any PHY interface, including MII, RMII, GMII and RGMII
- SGMII / QSGMII supported (connected through internal GMII to the AMD LogiCORE SGMII / QSGMII IP core)
- AXI-Stream interface (8-bit data at 125 MHz, 10/100/1000 Mbps)
Redundancy - HSR/PRP (IEC 62439-3 Ed.4.0)
- HSR operating modes (changeable at run time): Mode H (HSR tag forwarding, standard), Mode M (mixed forwarding), Mode N (no forwarding), Mode T (transparent forwarding), Mode U (unicast forwarding) and Mode R (for RSTP bridge connection)
- PRP operating mode: duplicate discard (standard) and duplicate accept (for testing)
- RedBox operating mode: HSR-SAN, HSR-PRP and HSR-HSR modes
- Redundant proxy node table and duplicate discard table, both with configurable size
- Between ring portsCut-through forwardinggives very low latency independent of frame size
Time synchronisation
- IEEE 1588 (PTPv2) stateless transparent clock (SLTC) - Layer 2 and P2P support
- IEEE 1588 hybrid clock (HC) slave operation - PPS output, event timestamping (up to four channels) and alarm detection (up to four types)
- IRIG-B master output (IRIG 200-04 compliant, DCLS modulation, IEEE 1344 extensions, with a built-in SPI/QSPI/MICROWIRE-compatible DAC controller)
Traffic management and QoS
- Per-port ingress frame filtering by destination MAC and EtherType
- Custom MAC filtering: up to 16 destination MACs and 10 source MACs
- Standard frames (1518 bytes) and jumbo frames up to 9 kB
- QoS: up to eight priority queues per port, with classification and remapping by PCP (802.1p), DSCP TOS or EtherType
- Per-port ingress rate limiting and strict priority scheduling
Management and deliverables
- Per-port MAC and switch statistics, plus an I2C master for external EEPROM configuration
- Deliverables: encrypted or source RTL, drivers, configuration API and software stack, plus full documentation
- Options: Networking Testbench Suite (NTS) and AMD Vivado sample designs
- A GUI is provided for AMD Vivado Design Suite. An evaluation version (encrypted, time-limited) is available.
Evaluation on real hardware
- As evaluation modules pre-programmed with this IP coreSMARTmpsoc Brick, SMARTzynq Brick is available.
- you can verify HSR/PRP behaviour on real hardware before integrating it into your own FPGA.
Related products in the SoC-e SocTek networking IP core line
Other models in the same product line. Select by logic capacity, I/O count and temperature grade.
Ask about HPS — HSR/PRP Switch
HPS — HSR/PRP Switch is handled in Japan by Positive ONE Group, value-added reseller (VAR) for SoC-e of Spain. We confirm availability, quantities and pricing with the manufacturer before replying.
Because pricing depends on configuration and quantity, we do not publish prices or stock levels on this site.Request an individual quotation