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ETSN — Endpoint TSN

VHDL IP for FPGAs

TSN endpoint IP providing deterministic Ethernet termination.

ETSN — Endpoint TSN — TSN endpoint IP core
FPGA
VHDL IP for FPGAs
Memory
Temp
Size
VHDL IP
Overview

Overview

ETSN — Endpoint TSN is a soft IP in the SocTek IP core range from SoC-e, supporting TSN (Time-Sensitive Networking). TSN is a family of IEEE 802.1 standards that deliver guaranteed bandwidth and bounded latency over standard Ethernet, and it is seeing growing adoption in real-time domains such as industrial automation, automotive and aerospace. Implementing ETSN — Endpoint TSN on an FPGA lets you build these capabilities into your own product.

Positive ONE Group supports ETSN — Endpoint TSN end to end: choosing the right option, providing evaluation versions, helping you obtain reference designs, and supply and long-term availability in volume production. We work in English and Japanese.

Diagram

Appearance and internal structure

INTERNAL BLOCK DIAGRAM — ETSN — Endpoint TSNIngressClassifierTAS802.1QbvPreempt802.1QbuEgressQueuesFPGA FABRIC (VHDL IP)
Internal block diagram (prepared by Positive ONE)
SYSTEM CONNECTION — ETSN — Endpoint TSNUser logicYour logicETSNIP CoreEthernetNetworkAXIMAC
System connection diagram
IP specification

Key specifications

ETSN — Endpoint TSN key specifications
Supported standardsIEEE 802.1AS, 802.1Qav, 802.1Qbv, 802.1CB
Supported FPGA familiesAMD (Xilinx)
Speed100M / 1G / 10G
Port configurationEndpoint (one port)
Operating modeTSN Talker / Listener
Latency and forwardingTime-aware scheduling (802.1Qbv)
InterfacesAXI4-Lite / AXI4-Stream; GMII (1G), USXGMII / 10GBASE-R (10G)
LicenceProject licence, evaluation version available
DeliverablesNetlist or encrypted RTL, sample design and user manual
EDA integrationVivado IP Integrator

Actual resource usage (LUT, FF, BRAM), supported devices and speed grades vary by configuration. Tell us your requirements and we will give concrete figures with the quotation.

Interfaces and applications

Main interfaces and applications

Main interfaces

  • USXGMII / 10GBASE-R (10G connection)
  • GMII / RGMII (1G connection)
  • AXI-Stream (internal FPGA interconnect)

Typical applications

  • Deterministic communication in industrial automation (IEC/IEEE 60802)
  • Automotive networks (IEEE 802.1DG)
  • Airborne networks (IEEE 802.1DP)
  • Synchronised communication for robotics and motion control
FAQ

Frequently asked questions

How is this IP core delivered?

It is licensed per project. An evaluation version is available so you can confirm operation on your own FPGA before production. Deliverables are a netlist or encrypted RTL, a sample design and the user manual.

Which FPGAs can ETSN — Endpoint TSN be used with?

The target FPGA is AMD (Xilinx). Supported design tools are AMD Vivado. If your target device is already fixed, please ask us to confirm.

How is ETSN — Endpoint TSN delivered and licensed?

It is supplied as a VHDL source IP core with a technical support package. Extensive synthesis-time and run-time parameters let you optimise FPGA resource usage, and custom development is available.

How can I evaluate ETSN — Endpoint TSN?

An encrypted, time-limited evaluation licence is available (terms on request). The evaluation hardware is SMARTzynq Brick / SMARTmpsoc Brick / MEZU-A7G8 Brick. Please contact us to discuss the configuration.

What is the price and lead time for ETSN — Endpoint TSN?

Pricing for ETSN — Endpoint TSN depends on configuration, licence type, quantity and any customisation, so we quote individually. Tell us your application and quantity in the form on this page and our engineers will confirm the specification and come back with a quotation and lead time.

Ask about ETSN — Endpoint TSN

ETSN — Endpoint TSN is handled in Japan by Positive ONE Group, value-added reseller (VAR) for SoC-e of Spain. We confirm availability, quantities and pricing with the manufacturer before replying.

Because pricing depends on configuration and quantity, we do not publish prices or stock levels on this site. Request an individual quotation

Design environment

Target FPGA
AMD (Xilinx)
Design tools
AMD Vivado
Evaluation
Encrypted, time-limited version (terms on request)
Evaluation hardware
SMARTzynq Brick
SMARTmpsoc Brick
MEZU-A7G8 Brick