IP core (implemented in your own FPGA), embedded module (mounted on your board), expansion card (plugged into a PC), or ready-built equipment (simply installed). Development effort and flexibility differ greatly between them.
See how to choose a deployment option →MRS — Managed Redundant Switch
Managed Ethernet switch IP with redundancy, for high-availability networks.
Overview
MRS — Managed Redundant Switch is a soft IP in the SocTek IP core range from SoC-e, aimed at industrial Ethernet. Implementing it inside an FPGA lets you build high-availability, low-latency networking into your own product.
Positive ONE Group supports MRS — Managed Redundant Switch end to end: choosing the right option, providing evaluation versions, helping you obtain reference designs, and supply and long-term availability in volume production. We work in English and Japanese.
Appearance and internal structure
Key specifications
| Supported standards | IEC 62439-3 plus IEEE 802.1Q (HPS and MES combined) |
|---|---|
| Supported FPGA families | AMD Zynq UltraScale+, Zynq-7000 and Kintex, plus Intel |
| Speed | 10/100/1000 Mbps |
| Port configuration | HSR/PRP ring plus standard ports (up to 32, within resource limits) |
| Operating mode | Redundancy plus managed switching with DLR / MRP / STP |
| Latency and forwarding | Cut-through on ring ports, store-and-forward on standard ports |
| Interfaces | AXI4-Lite / MDIO / COE / UART, (R)GMII |
| Licence | Project licence, evaluation version available |
| Deliverables | Netlist or encrypted RTL, sample design and user manual |
| EDA integration | Vivado IP Integrator |
Actual resource usage (LUT, FF, BRAM), supported devices and speed grades vary by configuration. Tell us your requirements and we will give concrete figures with the quotation.
Main interfaces and applications
Main interfaces
- Ethernet MAC / PHY interface
- AXI (internal FPGA interconnect)
Typical applications
- Core processing in embedded systems
- Industrial, instrumentation and communications applications
Frequently asked questions
How is this IP core delivered?
It is licensed per project. An evaluation version is available so you can confirm operation on your own FPGA before production. Deliverables are a netlist or encrypted RTL, a sample design and the user manual.
Which FPGAs can MRS — Managed Redundant Switch be used with?
Built on open standards, it can be implemented on several FPGA families, primarily AMD/Xilinx. It is supplied as VHDL source and works with EDA tools such as AMD Vivado.
How is MRS — Managed Redundant Switch delivered and licensed?
It is supplied as a VHDL source IP core with a technical support package. Extensive synthesis-time and run-time parameters let you optimise FPGA resource usage, and custom development is available.
How can I evaluate MRS — Managed Redundant Switch?
You can verify operation on real hardware using evaluation kits, sample designs and SoC-e’s SocTek modules or RelyUm equipment. Some configurations allow plug-and-play evaluation.
What is the price and lead time for MRS — Managed Redundant Switch?
Pricing for MRS — Managed Redundant Switch depends on configuration, licence type, quantity and any customisation, so we quote individually. Tell us your application and quantity in the form on this page and our engineers will confirm the specification and come back with a quotation and lead time.
Related products in the SoC-e SocTek networking IP core line
Other models in the same product line. Select by logic capacity, I/O count and temperature grade.
Ask about MRS — Managed Redundant Switch
MRS — Managed Redundant Switch is handled in Japan by Positive ONE Group, value-added reseller (VAR) for SoC-e of Spain. We confirm availability, quantities and pricing with the manufacturer before replying.
Because pricing depends on configuration and quantity, we do not publish prices or stock levels on this site.Request an individual quotation