Home / Product list / PTP Ordinary/Boundary Clock‹ PrevNext ›
SoC-e / ip

PTP Ordinary/Boundary Clock

VHDL IP for FPGAs

IEEE 1588v2 Ordinary and Boundary Clock IP (L2/L3, E2E/P2P) for high-accuracy synchronisation across the whole network.

PTP Ordinary/Boundary Clock — precision time synchronisation IP core
FPGA
VHDL IP for FPGAs
Memory
—
Temp
—
Size
VHDL IP
Overview

Overview

PTP Ordinary/Boundary Clock is a soft IP core in SoC-e’s SocTek range for precision time synchronisation. IEEE 1588 (PTP, Precision Time Protocol) achieves nanosecond-class synchronisation over a network, and PTP Ordinary/Boundary Clock performs timestamping in FPGA hardware, giving accuracy and jitter that software implementations struggle to match.

Positive ONE Group supports PTP Ordinary/Boundary Clock end to end: choosing the right option, providing evaluation versions, helping you obtain reference designs, and supply and long-term availability in volume production. We work in English and Japanese.

Diagram

Appearance and internal structure

CONCEPTUAL BLOCK DIAGRAM — PTP Ordinary/Boundary ClockRX TSTimestampPTPEngineServoClockPPS/ToDOutputFPGA FABRIC (VHDL IP)
Internal block diagram (prepared by Positive ONE)
SYSTEM CONNECTION — PTP Ordinary/Boundary ClockUser logicYour logicPTP Ordinary/Boundary ClockIP CoreEthernetNetworkAXIMAC
System connection diagram
IP specification

Key specifications

PTP Ordinary/Boundary Clock key specifications
Supported standardsIEEE 1588-2008 (OC/BC)
Supported FPGA familiesAMD (Xilinx)
Speed10/100/1000 Mbps
Port configurationOrdinary Clock and Boundary Clock configurations
Operating modeOC (tens of ns) / BC (multi-port boundary clock)
Latency and forwardingHardware timestamping
InterfacesAXI4-Lite, GMII
LicenceProject licence, evaluation version available
DeliverablesNetlist or encrypted RTL, sample design and user manual
EDA integrationVivado IP Integrator

Actual resource usage (LUT, FF, BRAM), supported devices and speed grades vary by configuration. Tell us your requirements and we will give concrete figures with the quotation.

Interfaces and applications

Main interfaces and applications

Main interfaces

  • PPS (1 pulse per second) output
  • ToD (Time of Day) output
  • GMII / RGMII (PTP frame processing)

Typical applications

  • Time synchronisation in power systems (substations and power plants)
  • Timestamp synchronisation across distributed measurement systems
  • Frequency and phase synchronisation for base stations and broadcast facilities
FAQ

Frequently asked questions

How is this IP core delivered?

It is licensed per project. An evaluation version is available so you can confirm operation on your own FPGA before production. Deliverables are a netlist or encrypted RTL, a sample design and the user manual.

Which FPGAs can PTP Ordinary/Boundary Clock be used with?

The target FPGA is AMD (Xilinx). Supported design tools are AMD Vivado. If your target device is already fixed, please ask us to confirm.

How is PTP Ordinary/Boundary Clock delivered and licensed?

It is supplied as a VHDL source IP core with a technical support package. Extensive synthesis-time and run-time parameters let you optimise FPGA resource usage, and custom development is available.

How can I evaluate PTP Ordinary/Boundary Clock?

An encrypted, time-limited evaluation licence is available (terms on request). The evaluation hardware is SMARTzynq Brick / SMARTmpsoc Brick / MEZU-A7G8 Brick. Please contact us to discuss the configuration.

What is the price and lead time for PTP Ordinary/Boundary Clock?

Pricing for PTP Ordinary/Boundary Clock depends on configuration, licence type, quantity and any customisation, so we quote individually. Tell us your application and quantity in the form on this page and our engineers will confirm the specification and come back with a quotation and lead time.

Ask about PTP Ordinary/Boundary Clock

PTP Ordinary/Boundary Clock is handled in Japan by Positive ONE Group, value-added reseller (VAR) for SoC-e of Spain. We confirm availability, quantities and pricing with the manufacturer before replying.

Because pricing depends on configuration and quantity, we do not publish prices or stock levels on this site. Request an individual quotation

Design environment

Target FPGA
AMD (Xilinx)
Design tools
AMD Vivado
Evaluation
Encrypted, time-limited version (terms on request)
Evaluation hardware
SMARTzynq Brick
SMARTmpsoc Brick
MEZU-A7G8 Brick